Failure Modes and Mechanisms Due to Wafer Properties and Processes (SE124-95-0)

SynopsisWith the continuous downscaling and increasing reliability requirements of ULSI devices, it is necessary to understand the failure modes and mechanisms in microelectronic integrated circuits (IC). The demand for performance and reliability of sub-100nm devices requires the engineers to understand how failure occur and hence, how failure can be traced back to the wafer material properties and manufacturing processes. This course details the various failure modes and the related mechanisms that occur in typical sub-100nm integrated circuits such as MOSFET, DRAM and flash memory.

This course aims to provide engineers with comprehensive knowledge about failure mode in semiconductor devices and how the failure is related to material properties and manufacturing processes. The course covers the following topics:

• Failure curve and failure periods, screening methods and its limitation, reliability factors and standards and test element group (TEG) evaluation;
• Failure due to crystal defect include silicon grown-in defects detection, the DRAM GOI, structure, isolation and short failures and improvement of silicon susbtrate;
• Lithography failures due to silicon susbtrate mechanical properties such as flatness, nanotopography, edge profile and backside morphology;
• Metal contamination which cause the junction leakage, oxide breakdown and pitting. Method to remove contamination such as applying gettering technology;
• Electric charge in oxide films. The various charges in oxide and process improvement. C-V measurement of threshold voltage change due to electric charge in oxide;
• Time-dependent-dielectric-breakdown (TDDB) model and failure rate prediction and improvement in flash memory;
• Hot carrier injection mechanisms, degredation effects and reliability in device;
• Negative-bias temperature instability (NBTI) mechanism and measurement include IC lifetime and reliability due to NBTI;
• Latch-up mechanism and evaluation methods. Device yield improvements due to latch-up failure;
• Soft error mechanism and error in DRAM. Test methods and methods to reduce soft error;
• Electromigration mechanism and failure model. Electromigration failure and suppression in interconnection.

What previous participants say about this course
Answers to the question 'What did you like most about this course'

• "Application on physics on wafer process. Basic physic theory is used in industry" - 14 Oct 09
• "Easily understandable" - 14 Oct 09
• "More understanding on failure on wafer/semiconductor due to the process" - 14 Oct 09
• "Process defect" - 14 Oct 09
• "Provide example re-explanation by using real life example. Easy to understand" - 14 Oct 09
• "The mechanism of failure" - 14 Oct 09
• "Material used is easy to understand" - 31 May 10
• "Lecturer explain very well to make us understand" - 31 May 10

What You Will Learn

• Failure curve, screening methods and reliability factors and standards.
• Device failures due to silicon substrate defects.
• Metal contamination and electric charge in oxide film.
• TDDB, hot carrier injection and NBTI in MOS devices.
• Latch-up, soft error and Electromigration in microelectronic devices.
• Advance wafer processes such as lithography, etching, CMP, CVD, metallization.
• Advance devices such as DRAM and flash memory.

Who Should Attend

• Process engineers
• QC/QA engineers
• Product engineers
• FA engineers
• Technical service engineers

PrerequisiteTechnical background with working experience in semiconductor devices and ICs.

Course MethodologyThis course is presented classroom style, with case studies to illustrate the concepts taught.

Course Duration3 days, 9am - 5pm

Course StructureDay 1

• Failure curve, screening methods and reliability factors and standards in microelectronic industries.
• Application and design of test elements group (TEG) for failure prediction
• Device failures include GOI integrity, structure and isolation failures due to crystal defect.
• Improvement of substrate material for yield improvement.

Day 2

• Lithography failures due to silicon substrate mechanical properties including: (i) flatness, (ii) Nanotopography (include effect on CMP), (iii) Edge roll and edge profile, (iv) Backside morphology (include effect on ESC chuck)
• Metal contamination and method to improve the substrate quality via gettering technology
• Electric charge in oxide film and the effect to device such as threshold voltage shift.
• The effect of time dependent dielectric breakdown (TDDB) on MOS devices. The prediction of TDDB and the failure modes in NAND flash memory.

Day 3

• Hot carrier injection and the mechanisms include the MOS lifetime. The application of hot carrier injection in flash memory.
• Device reliability and failure due to negative-bias temperature instability (NBTI) include the mechanism of NBTI and the interface.
• Latch-up in CMOS and its mechanism include the evaluation and improvement methods of latch-up.
• Soft error and the failure of devices due to soft error especially in RAM. Method to prevent soft error in devices.
• The mechanism of electromigration and the effect to the interconnection failure. The suppression of electromigration in devices.