FPGA-Based Digital System Design with VHDL (PR340)

Synopsis(This course is similar with another course entitled “FPGA-Based Digital System Design with HDL” where the latter is using Verilog HDL instead of VHDL. You may find the training flow the same, except using a different design language.)

Digital circuit design methodology has seen a drastic change in the last decade, with the introduction of electronic design automation (EDA) tools, hardware description languages (HDLs) such as VHDL / Verilog and programmable logic devices (PLDs) such as CPLD/FPGA.

This course provides an intensive learning on digital system design from VHDL programming, register transfer level design, VHDL testbench design, to the practical implementation of digital systems on Altera FPGA development board using VHDL design entry with EDA tool.

Course highlight
Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera Quartus II development software and ModelSim-Altera simulator.

What You Will Learn

• Design entry using VHDL language
• Register transfer level (RTL) design
• VHDL testbench design
• Practical use of electronic design automation (EDA) tools including Altera Quartus II and Mentor Graphics’s ModelSim in design entry, analysis, and simulation
• Practical design implementation and I/O interface on field-programmable gate array (FPGA) using VHDL

Who Should AttendTechnicians and engineers who are involved in design, product marketing, production, test and development of digital circuit design.

PrerequisiteBasic knowledge in digital electronics at diploma or degree levels.

Course MethodologyThe participants are taught design theories in classroom setting in the morning, followed by practical lab exercises in the afternoon on each day of the training. They will go through practical design experience using the Altera DE2 FPGA development board, together with the use of Altera Quartus II development software.

Course Duration3 days, 9am - 5pm

Course StructureVHDL Design for FPGA Implementation: Part 1
HDL based design flow, VHDL design and program structure, structural and behavioral programs, registers, latches, tristates, counters, adder/subtractors, multiplier, multiply-accumulators, multiplexers, RAMs, ROMs, shift registers, state machines

Lab Exercise 1
VHDL design entry, compilation, static timing analysis, input waveform entry, simulation, clock divider

VHDL Design for FPGA Implementation: Part 2
Hierarchical design, component declaration, component instantiation, concatenation, aggregates, slices of arrays, data type classification, enumeration types, type conversion, operators, sequential statements, concurrent statements

Lab Exercise 2
Basic I/O, pin assignment, programming device, counter designs

Register Transfers and Sequencing
Registers transfer operations, microoperations, algorithmic state machines

VHDL Testbenches
Purpose of testbench, three classes of traditional testbenches, general testbench methods, self verification methods, arrays for stimulus & results, TEXTIO for stimulus & results

Lab Exercise 3
ModelSim-Altera Simulations