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- 18 - 21 Oct 2010Location:DreamCatcher ConsultingPenang, Malaysia | Download Brochure
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FPGA-based Digital System Design with HDL (PR101-33-0)
Synopsis Digital Circuit Design methodology has seen a drastic change in the last decade, with the introduction of Electronic Design Automation (EDA) tools, Hardware Description Languages (HDL) such as VHDL / Verilog and Programmable Logic Devices (PLD) such as CPLD/FPGA.
This course provides an intensive learning on digital system design from Verilog HDL programming, register transfer level design, Verilog testbench design, I/O interfacing and control, to the practical implementation of digital systems on Altera FPGA development board using Verilog HDL design entry with EDA tool.
Course Highlight
Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera Quartus II development software and ModelSim-Altera simulator.
What previous participants say about this course
Answers to the question 'what did you like most about the course'
Figure below showing Altera Quartus II Software and DE2 Development Board
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What You Will Learn
Who Should AttendTechnicians and engineers who are involved in design, product marketing, production, test and development of digital circuit design.
PrerequisiteBasic knowledge in digital electronics at Diploma or Degree levels.
Course MethodologyThe participants are taught design theories in classroom setting in the morning, followed by practical lab exercises in the afternoon on each day of the training. They will go through practical design experience using the Altera DE2 FPGA development board, together with the use of Altera Quartus II development software.
Course Duration4 days, 9am to 5pm
Course StructureVerilog Design for FPGA Implementation: Part 1
HDL based design flow, Verilog design and module structure, Verilog lexical conventions, structural, dataflow, and behavioral models, registers, latches, tristates, counters, adder/subtractors, multiplier, multiply-accumulators, multiplexers, RAMs, ROMs, shift registers, state machines
Lab Exercise 1
Verilog design entry, compilation, static timing analysis, input waveform entry, simulation, clock divider
Verilog Design for FPGA Implementation: Part 2
Data types, concatenation, replication, slices of vectors, parameters, hierarchical design, module instantiation, primitive instances, operators, continuous assignments, always blocks, procedural statements, blocking vs. non-blocking assignments, combinational always block, clocked always block Lab Exercise 2 Basic I/O, pin assignment, programming device, counter designs
Register Transfers and Sequencing
Registers transfer operations, microoperations, algorithmic state machines
Verilog Testbench
Combinational circuit testing, sequential circuit testing, various testbench techniques: test data, simulation control, limiting data sets, apply synchronized data, synchronized display of results, interactive testbench, random time intervals, buffered data application
Lab Exercise 3
ModelSim-Altera Simulations
I/O core design
LCD module, PS/2 keyboard, VGA controller
Lab Exercise 4
PS/2 keyboard reading and displaying to LCD, VGA display control

