ASICs - Concept to Product (DS154-107-0)

SynopsisApplication Specific Integrated Circuit (ASIC) is a major topic of interest in the highly-competitive field of VLSI circuits where each industry player tries to outdo the other by introducing a niche and differentiated product ahead of the competition. While products assembled from off-the-shelf components are faster to reach the market, they ride on an already existing product wave. With ASICs, however, one can be the forerunner and tap into the initial and major chunk of the market window grossing high revenues. The exclusive design rights also provide an added advantage.

This course aims to provide a basic understanding of the ASIC development chain. It will enable your Design Engineer to understand the basics involved in various phases of the ASIC development chain, from A Request for Quote to Working Silicon, with an appreciation of how activities and decisions made in one phase affects another. It will also enable your Customer Support Engineering staff to provide an effective and proactive support to your ASIC customer. Product Development Engineers can also benefit from useful insight. This course also provides a well-structured guideline to Business Managers to be used as a reference for the ASIC business.

Course Highlight
The course is structured into modules. Short interactive workshops within the course facilitate in making this an interesting, interactive learning experience. Participants will be exposed to issues cited from real industry experience.

This course will be delivered by a senior VLSI consultant with extensive industry experience in supporting & managing ASIC projects on a global scale.

• “All the steps are gone through in the course” - 25 Sept 08
• “The course content was general enough for people with little or on background on ASIC design flow. I think this is a good introductory course” - 25 Sept 08

What You Will Learn

• Basics of ASIC Design Libraries, Design Flow
• Basics of Verification especially DFM/DFY
• Basics of Design for re-use and IPs, guidelines for Low Power design
• Insight into ASIC technology and market trends
• Overview of MPW/MRS
• Economics involved in ASIC development and Managing an ASIC Program with a broad understanding of various generic issues seen and tips on addressing them
• Effectively communicate with customers and support customers

Who Should Attend

• General IC & ASIC Design Engineers (1 - 4 years experience)
• Customer Support Engineers
• Product Development Engineers
• Sales & Marketing Professionals

PrerequisiteBasic engineering know-how. 1 - 2 years experience in IC design/support is preferable.

Course MethodologyThis course is conducted in a seminar room. The course will include brief interactive workshop-like sessions to encourage participation and facilitate learning. Each participant will receive a set of course material. There are no lab sessions.

The course is organized into modules to facilitate participants to attend a specific module(s) as per their interest/need. However to extract maximum benefit from the course, participation in all modules is recommended.

Course Duration3 days, 9am - 5pm

Course Structure1) Introduction to ASICs

• Standard cell based ASIC
• Semi custom ASIC and Full custom ASIC
• Brief outline of Design Flow
• Brief outline of Library

2) Design Library

• Definition
• Library Architecture (With basic introduction to SSIs, IOs, Memories, IPs; general circuits used like Flip flops, latches, combinational circuits, RAMs, ROMs etc. will be included)
• Library Cell Representations
• Cell views (logical description, timing information, derating data, capacitance information, power and area information)
• Global views (max capacitance, interconnect info, max power and derating information)
• Library Characterization - Standard load, trip points, parasitic caps, input slew rate, timing equation (predicting delay), example of predicting delay
• Library Validation
• Trends in Library architecture
• Power, speed optimization, drive, contents changing with technology and trends

3) Logic Simulation & Synthesis

• Simulation modes (behavioral, functional, static timing analysis, gate level simulation, transistor level simulation)
• Net capacitance
• Logic Systems (signal resolution, signal strength)
• How Logic simulation works
• Cell model (primitive, library, macro/IP), HDL Languages(Verilog, VHDL)
• SDF in simulation
• Delay models (types of delays: pin to pin delay, input slope delay model)
• Limitations of logic simulation
• STA
• Logic synthesis
• Verilog and synthesis
• Handling Delays
• Memory Synthesis
• Timing driven synthesis
• RTL coding guidelines

4) Floorplan, Placement & Routing, Finishing

• Floorplan: Goal, objective, I/O and Power planning, Core limited and pad limited design, Clock Planning
• Place & Routing, Finishing: Goals & Objectives, Timing driven placement/Physical Design flow, Information formats, Routing, Global & detailed routing, Clock routing, Power Routing, Back Annotation, Circuit extraction, Design checks, Mask preparation

• Need
• Functional Verification: Simulation, Formal Verification, Code coverage, Assertion Based Verification
• Timing Verification: STA, SSTA
• DFT: Scan : Full scan : Boundary scan, Faults, Fault models, Fault collapsing, IDDQ test, Fault simulation, ATPG, AT speed testing, BIST, Test logic insertion
• Physical Verification: DRC, LVS, Parasitic Extraction
• Design for Manufacturability/Design For Yield (DFM/DFY)

6) Design for Re-use & IPs

• What is IP, what is Design Re-use
• IPs (Driving factors, IP selection, IP verification, issues involved, generic portfolio)
• Concurrently developed in-house IPs
• Practical Design Re-use approach and essentials
• IP market landscape
• Industry bodies

7) Low Power DesignGuidelines

• Sources of power dissipation
• Low power design techniques and methodologies (levels of low power optimization)
• Low power design tools classification
• Guidelines for low power design

8) ASIC construction & Managing an ASIC program

• Basic economics involved in ASIC development
• ASIC Program Flow
• Key factors to be considered at ASIC start up
• Selecting technology, library, IPs, package etc.
• Die size estimation, power estimation
• Design interfaces
• What is an ASIC program
• Different functions
• Documentation, check lists, sign-offs
• Issues seen during ASIC implementation
• Guidelines for effective ASIC program management

9) Multi Project Wafer Service/Multi Reticle Service

• What is MPW
• When to/Why/Who goes for MPW
• Generic MPW Flow model
• What is Multi Reticle Service
• Foundry Perspective (Project Scheduling, Capacity Planning, General Pricing considerations)

10) Trends in the ASIC arena

• Some definitions
• Shift in ASIC technology & the underlying reasons
• Insight into Structured ASICs/Platform ASICs: IPs used in Platform ASIC, Cell based ASIC vs. Platform ASIC, Some Industry examples illustrating the trend