Digital System Design - LEVEL I and LEVEL II (CP210)

Synopsis

The demand for engineers in communication-enabling technologies, who can contribute quickly upon graduation or entering the field, is increasing in tandem with the growth in communication industries and reduction in product time-to-market. Shortage of relevant skill sets are prevalent among young engineers due to the complexities of theories, lack of exposure to relevant industry tools and missing domain knowledge in various functions within the communication-enabling industries.

DreamCatcher Certification Program covers a comprehensive domain area in communication-enabling technologies, ranging from semiconductor materials and devices, circuit designs and tests, and, system integration, deployment, testing and commissioning. In collaboration with global technology partners and experts, DreamCatcher Certification Program is designed to help benchmark the expertise level of engineers working in these fields. It also provides an alternative development path for professionals to attain the relevant expertise to work in these challenging fields which see constant change of devices, systems, protocols and standards.

University typically emphasizes on the broad coverage of theories and concepts while on-the-job-training emphasizes on the ability to operate relevant industry tools. DreamCatcher Certification Program emphasizes on a balanced coverage of industry tools, domain knowledge and relevant theories and concepts for the development of specific domain expertise as illustrated below. This balanced approach will equip engineers with relevant skills to contribute more effectively when entering a specific technical field.



DreamCatcher Certification Program value propositions to young engineers and professionals are: 

• To gain exposure to the state-of-the-art technologies, industry tools and software 
• To gain expose to industry standard practices through case studies and projects 
• To acquire knowledge and skills through a structured and extensive curriculum designed by industry experts and endorsed by global technology leaders 
• To gain reassurance that his/her expertise meets industry-accepted standards, and that he/she has undertaken structured certification training program successfully, achieving the minimum benchmarked level. Therefore, certification serves as benchmark to expertise attained.

What You Will Learn

Upon successful completion of LEVEL I Certification, participants will be able 

• To have a strong overview of the domain area with appreciation of underlying concepts, processes, tools and techniques employed specifically to the domain; 
• To perform a prescribed range of functions involving known routines and procedures within the domain; 
• To perform in a range of varied activities where there is a clearly defined choice of actions with limited complexity and limited range of applicable options to be applied, and;
• To have the relevant foundation to further acquire advanced skills within the domain.

Upon successful completion of LEVEL II Certification, participants will be able 

• To have an in-depth understanding and appreciation of concepts, processes, tools and techniques employed specifically to the domain; 
• To perform analysis involving complex routines and procedures within the domain; 
• To perform technical decision-making activities involving a range of trade-off possibilities for technical task with limited complexity and limited range of applicable options to be applied; and 
• To have the relevant in-depth understanding of the domain to further undertake experiential learning through solving technical challenges with higher complexities.

Who Should Attend

Fresh graduates or engineers interested to advance their technical career in the fields of communication-enabling technologies.

Prerequisite

For admission to LEVEL I Certification, candidates should have tertiary education level in relevant fields as follows: 

• Electrical and Electronic Engineering, 
• Telecommunication Engineering, 
• Microelectronics Engineering, 
• Computer Engineering, 
• Software Engineering,

OR

3 years working experience in the relevant fields with other technical degree. 


For admission to LEVEL II Certification, candidates should have tertiary education level in relevant fields as follows:  

• Electrical and Electronic Engineering, 
• Telecommunication Engineering, 
• Microelectronics Engineering, 
• Computer Engineering, 
• Software Engineering,

AND

3 years working experience in the relevant fields and pass pre-entry assessment, OR completed LEVEL I Certification.

Course Methodology

The participants are first taught the relevant theories in a classroom setting. The concepts are re-enforced through tutorial and case studies of how the theories are applied in real-life. Demonstration using the state-of-the-art design and testing tools will be carried out to illustrate various principles and techniques.

The participants are then taught the use of software and hardware tools which are de-facto for the chosen domain area. The concepts are re-enforced through practical exercises on the use of the tools to test and design relevant applications.

Having acquired both practical skills in tools and pre-requisite knowledge in the domain area, the participants are required to apply their knowledge through individual or group project work. The participants will then present their project, demonstrating desired performance vs actual result.

Course Duration

LEVEL I Certification
15 days, 7 hours/day, with a total contact of 105 hours

LEVEL II Certification
15 days, 7 hours/day, with a total contact of 105 hours

Course Structure

Level I Certification

Introduction to Logic Circuits (DSD01-01)
Logic gates, representations of digital logic, integrated circuits, levels of integration, digital logic families, CMOS circuits 

Design Methodology and CAD tools (DSD01-02)
Design entries, design abstraction levels, computer-aided design (CAD) tools, design and CAD flow using CPLD/FPGA, hierarchical design 

Review of Digital Logic Design (DSD01-03)
Combinational circuit analysis and synthesis, Karnaugh maps, encoders, decoders, tri-state outputs, multiplexers, adders, subtractors, multipliers, comparators, ROM, metastability, finite state machines (FSM): Mealy model FSM, Moore model FSM, state diagram, registers, counters, synchronous design methodology, clock issues, asynchronous inputs, design hazards 

Pipelined Design (DSD01-04)
Design optimization techniques: loop unrolling, chaining, multicycling; pipelining techniques: process pipelining, loop pipelining, functional unit pipelining, distributed controller 

Programmable Logic Devices (PLD) (DSD01-05)
Implementation platforms, cell-based, array-based, PLA, PAL, FPGA, Altera Cyclone II architecture 

Verilog Design for FPGA Implementation (DSD01-06)
HDL based design flow, Verilog design and program structure, structural and behavioral programs, registers, latches, tristates, counters, adder/ subtractors, multiplier, multiply-accumulators, multiplexers, RAMs, ROMs, shift registers, state machines, Verilog data types, concatenation, slices of vectors, parameter, hierarchical design, module instantiation, operators, concurrent statements, procedural statements, blocking vs non-blocking statements 

Register Transfers and Sequencing (DSD01-07)
Registers transfer operations, microoperations, register transfer structures, Register cell design, buses, control unit, algorithmic state machines, and hardwired/microcode control, microprogrammed control 

Core Design Guidelines (DSD01-08)
General design guidelines: reset, clocks, buses, tri-state, memories, coding for synthesis, core I/O ports, Verilog design guidelines, multiclock designs, I/O core design case studies

Design Project (DSD01-09)
Creative gaming using Verilog design: To sharpen students’ design skills where they will be able to design a digital system and implement in an FPGA, and to expose students to go through digital system design flow from initial design concept, system-level design, design entry, to implementation 
 
Software Tools Used
Altera Quartus II

Hardware Tools Used
Altera DE2 board, VGA monitor, PS/2 keyboard


Level II Certification

Computer Design (DSD02-01)
Datapath, arithmetic logic unit, control unit, instruction set architecture 

Verilog Testbench (DSD02-02) 
Combinational circuit testing, sequential circuit testing, various testbench techniques: test data, simulation control, limiting data sets, apply synchronized data, synchronized display of results, interactive testbench, random time intervals, buffered data application 

Advanced Verilog Design Techniques (DSD02-03)
Verilog basic concepts review, writing synthesizable Verilog, instantiating logic, coding state machines, optimizing designs for FPGA 

Case Studies of Selected I/O interfaces (DSD02-04)
Ethernet technologies and operations, OSI model relationship, signal and data encoding, 10BASE-T features, 100BASE-TX features, Gigabit ethernet, ethernet frame format;
DDR SDRAM Devices and Operations, Power Up initialization, Commands Operations, SDRAM Initialization, Operation Mode and Timings, DDR2 SDRAM Devices and Operations, ODT and OCD features, Power Up initialization, Commands Operations, Operation Mode and Timings, DDR3 SDRAM, Pseudo Open Drain, Signal Swing 

Timing Closure (DSD02-05)
Netlist optimizations, assignment editor, synthesis attributes & directives, timing analysis, single clock analysis, timing assignments 

Analysis and Debugging Tools (DSD02-06)
Power Analysis with PowerPlay, Quartus II debugging tools: SignalProbe incremental routing, In-System Sources and Probes, SignalTap II embedded logic analyzer, Logic Analyzer Interface, Chip Planner & Resource Property Editor 

Embedded System Design Using Nios II (DSD02-07) 
Nios II Hardware Development, Nios II Software Development, Nios II Software Debug, RTL Simulation, System Interconnect Fabric, Custom Instructions, Configuring the Development Board, SOPC Builder Tool Review and Usage, Avalon-MM Slaves, Avalon-MM Masters, Developing Programs for Nios II, Nios II Embedded Systems, Advanced Debug Features, Hardware Acceleration and Direct Memory Access, Introduction to SOPC Builder Device Drivers, Nios II Software Components 

Design Project (DSD02-08) 
Embedded system design: To sharpen students’ design skills where they will be able to design a digital system and implement in an FPGA, and to expose students to go through digital system design flow from initial design concept, system-level design, design entry, to implementation

Software Tools Used
Altera Quartus II, ModelSim-Altera, Nios II EDS

Hardware Tools Used
Altera DE2 board, VGA monitor, PS/2 keyboard