SynopsisJob camp (JC) offerred by Multimedia Development Corporation (MDeC) is designed specifically for any Knowledge worker who wants to improve or expand their current ICT skills and knowledge. This program seeks to help knowledge workers with the support and access to courses and trainings to stay aligned with the current needs of the ICT industry.
DreamCatcher Consulting has been appointed by MDeC to offer programs in engineering tracks namely VLSI, DSP, and RF.
The general entry requirement for the program is Bachelor or Master Degree in Electrical and Electronics Engineering. Upon completion of the training program, participants are expected to acquire skill sets required to meet existing vacancies in the industry.
Program Highlight
- coaching from experienced academic instructors as well as engineers from industry
- substantial lab exercises to ensure participants have ample opportunities for hands-on
- use of leading Electronic Design Automation (EDA) tools for VLSI digital system design, verification, and implementation activities
Program Details
- Each course is 23 days in duration
- Courses are held in Kuala Lumpur or Penang
- Course fees are fully borne by MDeC
Registration
Fill up the registration form and attach with:
- Passport-sized photo
- Photocopy of IC
- Photocopy of university certificate or transcript
Enquiries
Visit http://dreamcatcher.asia/jc.htm for full details.
What You Will Learn1) Necessary technical soft skills for engineers to adapt from the university environment to real life technical working environment. These skills are:- Technical writing
- Technical presentation
- Creative problem solving - Triz
2) Pre-requisite knowledge in VLSI digital system. These include:
- Basics of digital system
- Design of combinational circuits
- Design of sequential circuits
- Design of pipelining systems
3) Hands-on experience in creating digital system design using Verilog HDL language. These include:
- Data path and control unit design of digital logic.
- Register-transfer level (RTL) design of digital systems.
- I/O interface designs
4) Practical skills in using programmable logic devices and the associated Electronic Design Automation (EDA) tools. These include:
- Practical use of Electronic Design Automation (EDA) tools in design entry, analysis, and simulation.
- Practical design implementation on Field Programmable Gate Array (FPGA) using Verilog HDL.
Who Should AttendAvailable K-Workers who are looking for practical skills in preparation for a technical career in VLSI industry such as:
- Design and Development Engineer
- Validation Engineer
- CAD Engineer
- Test Development Engineer
- System Integration Engineer
- etc
Prerequisite- Malaysian citizens
- Diploma/Degree holders in ICT-related fields
- Available K-Workers (currently unemployed, in-between jobs, changing fields, retrenched) with Bachelor or Master Degree in Electrical and Electronics Engineering.
- CGPA 2.5 or above
Course MethodologyThe participants are first taught the digital design theories in a classroom setting with the aid of EDA tools. The concepts are re-enforced through tutorial and design drills of how to build various digital modules. Design capture and simulation will be performed to strengthen the knowledge.
The participants will then be taught intensively the Verilog language. Synthesizable Verilog coding is stressed. This is tightly coupled with practical design drills using the Altera Quartus II development software and actual implementation in Altera Cyclone II FPGA on Altera DE2 Board.
Having acquired both pre-requisite knowledge and practical design skills using language and tool in the subject area, the participants are required to design a digital system as design project work. The design will be implemented on FPGA to demonstrate actual functionality.
Software Tools Used
- Altera Quartus II
- ModelSim-Altera
Hardware Tools Used
- Altera DE1/DE2 development board
- Personal Computer
Course Duration23 days, 9am - 5 pm
Course StructureModule 1 : Technical soft skills (3 days)
- Technical writing
- Technical presentation
- Creative problem solving
Module 2 : Digital Design Fundamentals (6 days)
- Introduction to Logic Circuits Logic gates, representations of digital logic, integrated circuits, levels of integration, digital logic families, CMOS circuits
- Design Methodology and CAD tools Design entries, design abstraction levels, computer-aided design (CAD) tools, design and CAD flow using CPLD/FPGA, hierarchical design
- Combinational Circuits Fundamentals of Boolean algebra, switching functions, truth tables, algebraic forms of switching functions, derivation of canonical forms, combinational circuit analysis and synthesis, Karnaugh maps, encoders, decoders, tri-state outputs, encoders, multiplexers, adders, subtractors, multipliers, comparators, ROM
- Sequential Circuits Metastability, flip-flops, finite state machines (FSM): Mealy model FSM, Moore model FSM, state diagram, registers, counters, state machines, synchronous design methodology, clock issues, asynchronous inputs, design hazards
- Pipelined Design Design optimization techniques: loop unrolling, chaining, multicycling; pipelining techniques: process pipelining, loop pipelining, functional unit pipelining, distributed controller
- Programmable Logic Devices (PLD)
- Implementation platforms, cell-based, array-based, PLA, PAL, FPGA, Altera Cyclone II architecture
- Altera Quartus II Demo Schematic design entry, input waveform entry, compilation, simulation, pin assignment, programming, introduction to Altera DE2
Module 3 : Verilog HDL Design and Simulation for FPGA Implementation (6 days)
- Verilog Design for FPGA Implementation HDL based design flow, Verilog design and program structure, structural and behavioral programs, registers, latches, tristates, counters, adder/ subtractors, multiplier, multiply-accumulators, multiplexers, RAMs, ROMs, shift registers, state machines o Verilog data types, concatenation, slices of vectors, parameter, hierarchical design, module instantiation, operators, concurrent statements, procedural statements, blocking vs non-blocking statements
- Register Transfers and Sequencing Registers transfer operations, microoperations, register transfer structures Register cell design, buses control unit, algorithmic state machines, and hardwired/microcode control, microprogramd control
- I/O core design LCD module PS/2 keyboard/mouse VGA controller
- Altera Quartus II Demo Verilog design entry, compilation, static timing analysis
Module 4 : Design Project (7 days)
- Creative multimedia gaming applications
Module 5 : Final Assessment (1 day)
