MSC Malaysia Job Camp - VLSI Design Methodology and Implementation (CP093)

SynopsisJob camp (JC) offerred by Multimedia Development Corporation (MDeC) is designed specifically for any Knowledge worker who wants to improve or expand their current ICT skills and knowledge. This program seeks to help knowledge workers with the support and access to courses and trainings to stay aligned with the current needs of the ICT industry.

DreamCatcher Consulting has been appointed by MDeC to offer programs in engineering tracks namely VLSI, DSP, and RF.

The general entry requirement for the program is Bachelor or Master Degree in Electrical and Electronics Engineering. Upon completion of the training program, participants are expected to acquire skill sets required to meet existing vacancies in the industry.

Program Highlight

• coaching from experienced academic instructors as well as engineers from industry
• substantial lab exercises to ensure participants have ample opportunities for hands-on
• use of leading Electronic Design Automation (EDA) tools for various VLSI design, verification, and analysis activities

Program Details

• Each course is 23 days in duration
• Courses are held in Kuala Lumpur and Penang
• Course fees are fully born by MDeC

Registration
Fill up the registration form and attach with:

• Passport-sized photo
• Photocopy of IC
• Photocopy of university certificate or transcript

Enquiries

• Phone: 04-640 7119 or
• E-mail: jc@dreamcatcher.com.my

Visit http://dreamcatcher.asia/jc.htm for full details.

What You Will Learn1) Necessary technical soft skills for engineers to adapt from the university environment to real life technical working environment. These skills are:

• Technical writing
• Technical presentation
• Creative problem solving - Triz

2) Pre-requisite knowledge in VLSI technology. These include:

• VLSI design flow
• IC fabrication process
• PC platform

3) Hands-on experience in VLSI system design in various levels of design abstractions. These include:

• Verilog HDL design
• Logic gate-level design
• Transistor-level design
• VLSI layout design

4) Practical skills in using Electronic Design Automation (EDA) tools for various VLSI design, verification, and analysis activities. These include:

• Logic and circuit design entries
• Physical design entry
• RTL (Register Transfer Level) simulation
• Logic synthesis
• Formal verification
• Place and route
• Parasitic extraction
• Timing analysis
• Power analysis
• Spice simulation
• Physical verification

Who Should AttendAvailable K-Workers who are looking for practical skills in preparation for a technical career in VLSI industry such as:

• Design and Development Engineer
• Validation Engineer
• CAD Engineer
• Test Development Engineer
• System Integration Engineer
• etc

Prerequisite

• Malaysian citizens
• Diploma/Degree holders in ICT-related fields
• Available K-Workers (currently unemployed, in-between jobs, changing fields, retrenched) with Bachelor or Master Degree in Electrical and Electronics Engineering.
• CGPA 2.5 or above

Course MethodologyThe participants are first outlined the VLSI design and verification flow, IC fabrication process, and PC platform overview to give the overall picture and trends of the engineering activities in semiconductor industry, particularly that involved high-end digital VLSI devices like microprocessor.

The participants will then be taught each of the major design, analysis, and verification activities in VLSI design flow involving various design abstraction levels from RTL, gate level, transistor level, down to VLSI layout. This is to prepare the participants to fit in one of these VLSI design activities in their future careers. Understanding all the various portions of the design flow is essential since each of the flow are correlated each other.

Besides teaching the VLSI design theories, lab exercises using the start-of-the-art EDA tools will be performed to provide hands-on experiences to the participants. EDA tools used include functional design tools like Altera Quartus II, simulation tools like ModelSim and LTspice, design synthesis tool from Synopsys, and layout tool like Magic VLSI Layout Tool. For each module of the course, participants will be assessed by milestone achievement of lab exercises and MCQ test at the end of each module.

Software Tools Used

• Altera Quartus II
• Mentor Graphics - ModelSim
• Synopsys's EDA tool suite
• LTspice
• Magic VLSI Layout Tool

Hardware Tools Used

• Altera DE1/DE2 development board
• Personal Computer

Course Duration23 days, 9am - 5pm

Course StructureModule 1 : Technical soft skills (3 days)

• Technical writing
• Technical presentation
• Creative problem solving

Module 2 : VLSI Overview (4 days)

• Logic Simulation & Synthesis
• Floorplan, Placement & Routing, Finishing
• Verification
• Low Power Design
• IC Fabrication Process
• PC Platform Overview

Module 3 : Functional Design (4 days)

• Verilog Design for Synthesis
• Register Transfers and Sequencing
• Verilog Testbench

Module 4 : Logic Design (4 days)

• Combinational Logic Design
• Sequential Logic Design
• Logic Design Flow
• Standard Cell Design Style
• Logic Synthesis
• Formal Verification/Equivalent Checking
• Placement
• Clock Tree Synthesis
• Transistor/Gate Sizing
• Routing
• Parasitic Extraction
• Timing Concepts
• Design for Power

Module 5 : Circuit Design (5 days)

• Semiconductor Materials and Devices
• Single Stage Amplifier
• Integrated Devices and Layout Considerations
• Current Mirrors/Active Load
• Bias Circuits
• Operation Amplifiers
• Feedback Theory
• Voltage-mode and current-mode Voltage Reference
• Compensation
• Power-On Reset

Module 6 : Physical Design (3 days)

• IC Design Flow and Layout
• Layout Quality
• Layout Hierarchy Concept
• Auto Place & Route, Custom Layout Overview
• Electronic Discharge and Latch Up
• Full Chip Integration
• Tape Out