Design for Testability (DfT) Strategies for Mixed Signal Systems (AC120-100-0)

SynopsisIntegrated electronic systems are increasing in complexity, speed and functionality. A consequence is that both analogue functionality and behavior is becoming increasingly dominant impacting on both the design and manufacturing flows. Testability is a core challenge here for both the design community in the context of delivering testable designs and the manufacturing process where discrete, continuous and sampled waveforms need to be generated, captured and processed at increasing clock speeds and resolution.

This course will focus on the design process with the objective of delivering the knowledge designers need to understand the source of failure and degradation in state-of-the-art mixed signal systems and build reliable and testable designs through an understanding of the test process and methodologies, functions and design rules to control both test costs and optimize test coverage. Both System-on-Chip and System-in Package implementations will be covered.

The first 2 days of this course will focus on the design hierarchy and the test process. At the process and transistor level, failure and degradation mechanisms together with methodologies and techniques for assessing the electrical impact will be addressed together with methods of minimizing the probability of occurrence. At the cell and macro level, test support and assess techniques will be explored together with bespoke test strategies for a range of functions ranging from asynchronous interfaces, gain stages and filters to MEMS components. At the system level, methods of optimizing the interface to the tester will be addressed including the use of standardized test access structures such as boundary scan extensions.

The second 2 days will focus on converter and clock control functions with conventional test strategies, design for testability techniques, embedded test, self-test solutions and on-line techniques addressed. On day 3, international roadmaps for converter and PLL embedded test and Design for Testability strategies will be reviewed followed by training in the range of test strategies and performance specifications used to both characterize designs and screen product in today's manufacturing industry. Day 4 will focus on Built-in-Self Test strategies for a range of converter technologies and PLL structures together with proposals for on-line test, self compensating and self-repair techniques.

What You Will Learn

• Process awareness - source of failures and degradation
• Fundamentals of measurement techniques (generating and capturing continuous and sampled data)
• Extended design rules for transistor level design and layout
• Bespoke test strategies for mixed signal functions
• Design for testability functions at macro and systems levels of the design hierarchy
• Fault simulation and Failure Mode and Effect Analysis techniques
• Embedded test strategies including self-test and on-line test techniques
• State-of-the-art solutions in embedded test for converters and PLL's

Who Should AttendTechnicians, engineers, circuit designers, and managers involved in design, testing or reliability of SoC and SiP based mixed signal systems including:

• Design engineers
• Test engineers
• Reliability engineers
• Yield analysis engineers
• Product engineers
• FA engineers
• Application engineering

PrerequisiteParticipants should have a basic background and understanding of semiconductor technologies and some circuit design basics. Analogue design and engineering expertise will not be assumed as a optional tutorial in analogue engineering will be made available. Previous familiarity in the design and test engineering domain will be advantageous in maximizing the impact of the course on the participant. Nonetheless crucial concepts will be reviewed as needed.

Course MethodologyThis course is presented in an interactive classroom style utilizing lecture, open discussion, and examples.

Course Duration4 days, 9am - 5pm

Course StructureDay 1

Mixed Signal DfT fundamentals

• Roadmaps and trends in DfT
• SoC and SiP test challenges
• Faults, defects and degradation in modern processes
• Layout and transistor level DfT techniques
• Current (IDDX) and Voltage measurement DfT support
• Fault modeling and FMEA processes
• DfT for MEMS and non-CMOS functions

Day 2

System Level DfT

• Mixed Signal test specifications
• Mixed Signal measurement and test techniques
• Digital DfT strategies for Mixed Signal Applications
• Test Access & Control architectures
• DfT solutions for high speed interfaces
• Gain control and filter DfT solutions
• On-chip signal generation and response analysis
• On-line test strategies

Day 3

Converter & PLL Design for Testability Strategies

• Roadmaps and trends in converter and PLL embedded test
• Test specifications across application domains
• Conventional test strategies & DfT approaches
• Test time, outgoing quality and measurement challenges

Day 4

Converter & PLL embedded Test Strategies

• Embedded tester strategies for converter & PLL test
• Partial & Full Self-Test
• Embedded Test for High Resolution Converters
• Self Calibration, Self Repair and Fault Tolerance Concepts